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DigitalDesign

CYCU EE-304G Digital Design

        Dr. Yu-Kuen Lai
        ylai@cycu.edu.tw
Department of Electrical Engineering
        

Course Objective

隨著超大型積體電路技術之進步,工程師所需設計的電路必須利用各種電腦輔助設計工具來協助高效率的設計工作。本課程之教學目標乃在 使同學們俱備數位電路設 計之基礎觀念,訓練同學們撰寫硬體描述語言與實體電路合成之能力,並提供同學們有效使用電路模擬、電路合成及測試方面等各種電腦輔助設計工具。

Lecture Time

Tuesday 15:10~18:00 PM

Place

篤信 Room 305 

Office Hour

Room 507 at Electrical & Computer Engineering building (電學507), Tuesday 17400~15:00PM

Textbook 

"Verilog for Digital Design",   Frank Vahid , Roman Lysecky  2007  John Wiley and Sons Publishers  978-0-470-05262-4
"Digital Design", Frank Vahid  July 2006  John Wiley and Sons Publishers  978-0-470-04437-7

Reference Books

"Verilog Styles for Synthesis of Digital Systems" by David R. Smith and Paul D. Franzon, Prentice Hall, 2000, (ISBN:0-201-61860-5)
"HDL Chip Design" a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog,” by Douglas J. Smith, Doone Publications, 2000, (ISBN:0-9651934-3-8)
"Introduction to Computing Systems from Bits & Gates to C & Beyond", Yale N. Patt & Sanjay J. Patel

Course Schedule

We are going to present  the following  important topics in digital design based on the book chapters. 
  • Combinational Logic Design
  • Sequential Logic Design—Controllers
  • Datapath Components
  • Register-Transfer Level (RTL) Design
  • Hardware Description Languages


Date Topics Notes Other Links
09/16 Introduction  First day of class, Chapter 1 ppt
09/23 Combinational Logic Design Ch2 ppt
MB-EVL-X3S50AN-V11 Development Board
09/30
Introduction to Hardware Description Languages Ch2 ppt
ModelSim Tutorial
counter.v
tb_counter.v
10/07

Lab1
10/14 Sequential Logic Design Ch3 (Verilog 1)
ppt
10/21

EX2
10/28 Sequential Logic Design Ch3 (Verilog 2) ppt
HW1 due on 11/03@11:59pm
(1) Ex2.51, (2) Ex3.21
11/04


11/11 Midterm Exam 1:30~16:00pm @懷恩107
11/18 Midterm Discussions (Verilog 3)
11/25 Datapath Components
Project Discussion
FPGA Lab, Source Codes ppt
12/02 Datapath Components Ch4  (Verilog 4)
12/09 Register  Transfer Level (RTL) Sesign Ch5 ppt
12/16 Optimizations & Tradeoffs Ch6 ppt
12/23 Physical Implementation Ch7 ppt
12/30 Programmable Processor Ch8 ppt








01/06 Final Project Presentation 

01/06 Final Exam

EDA Tools

Xilinx
    Download FREE ISE 10.1 Webpack
    ISE Design Suite 10.1 Software Tutorials
    Design Suite Software Manuals and Help - PDF Collection manuals
 
MB-EVL-X3S50AN-V11 Development Board
      User's Guide
      Schematic
      Spartan-3AN FPGA Family Data Sheet

Mentor Graphic ModelSim 6.3
    Quick Reference Guide
    SE Tutorial
    

Tutorials

    ModelSim Basic Simulation Flow

Lab and Homework Assignments

    Students work in group of two for lab and homework assignments.

Projects

Project Groups & Titles
Project Report Template
Project Grading Guideline



這個課堂專題設計的目的在於使同學們孰悉硬體描述語言與FPGA設計的實務經驗. 課堂專題設計使用Xilinx MB-EVL-X3S50AN-V11 實驗板, 約略分為以下幾個部分

1. 上數計數器課堂實例Xilinx FPGA燒錄練習

課堂中我們將使用一個簡易的上數計數器為例子讓同學觀察7段顯示器顯示的特性與演練Xilinx FPGA燒錄的程序.
2008/11/25演練完成

2. 視覺暫留

同學們將原有上數計數器的7段顯示器的例子、利用視覺暫留的技巧、使4位的7段顯示器能顯示出不同的數字(16進位)
2008/12/02設計完成

3. 簡易3位數加法計算機

擴增原有的設計, 使其可以成為簡易3位數加法計算機
2008/12/16設計完成

4. 數字鐘

擴增原有的設計, 使其可以成為俱有鬧鈴功能之數字鐘
2008/12/30設計完成


Grading

    Grade will be deducted 10%/day for late homework and assignment!
Midterm Exam 25%
Student Paper Presentation 25%
Labs & Homeworks 25%
Final Exam/Project 25%

Resources

           ASIC web site by Michael John Sebastian Smith
Cliff Cummings' Papers on Verilog
Synopsys User Group SNUG Proceedings
Verilog Resources 
Xemacs Verilog Mode
International Technology Roadmap for Semiconductors
Verilog.Net   Free Tools
LEON Open-Source Processor
National Semiconductor DP83820 10/100/1000 Mb/s PCI Ethernet Network Interface
Controller

Reference Guide & Tutorials

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