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NSD


CYCU EE-617R/407L

Network Systems Design

  • Course Objectives

Emerging network packet processing applications are shifting from routing and traffic management to those requiring inspection and modification of packet contents.  Examples include content-based billing and quality of service, layer-7 switching, and network security. The requirement to process every byte of a packet exceeds the already-substantial processing capabilities of high-speed networking equipment. 


Network processors (NPs) are application-specific processors that are optimized to bridge the gap between ASIC performance and the programmability of general-purpose processors.  Most current NPs employ multiple optimized cores, operating independently in MIMD (Multiple Instruction stream, Multiple Data stream) fashion, usually with multiple threads per processor to hide latency to memory. 

In this course, we are going to cover the network sytems design  and architecture exploration of the network processor. 
    • Upon finishing this course, students will be able to 
      • Understand the major hardware/software architecture for packet processing.
      • Gain the concepts of network systems design by using Network Processor
      • Understand  the Network Processor technology and operations.
  • Lecture Time & Place: 

Tuesday 14:10~17:00 PM

篤信305

  • Office Hour: 

電學507, Tuesday, 13:10~14:00PM

  •  Textbook

    • Network Systems Design Using  Network Processors (IXP2xxx Version) by Douglas Comer
  • Prerequisites

    • Students are recommended  to have basic knowledge of C programming language, microprocessor architectures, and computer networks. 
  • Course Schedule

Weeks Date Topics Notes Reading Assignments
1 02/17 Introduction on network systems and the Internet. The motivation of using Network Processors

NetFPGA Introduction
  1. EE617R
  2. Introduction
  3. NetFPGA Introduction
  • Chapter 1, 2  &11
2 02/24
No Class
3 03/3 Review of basic terminologies, protocols and  packet formats.
  1. Concepts
  2. Protocols&Format
  • Chapter 3
  • LAB1 is out today and due on 03/19
  • Please download this zip file for lab1
4 03/10 Conventional computer hardware architectures for packet processing.
  1. Router Architecture
5 03/17
(03/24 運動會)
Algorithms and Data Structures for packet processing.
  1. Algorithm
  • Chapter 5 & 6
  • CAIDA CoralReef  Introduction
  • LAB2: CoralReef  due on 03/24
  • PaperReview due on 04/
6 03/31
(04/07 春假)
Hardware & Software architectures for protocol processing,
NetFPGA 
  1. Algorithm
  • Chapter 7 
7 04/14 Overview of the Intel Network Processor
  1. IXP Intro
  • Chapter 17

8 04/20~24 Midterm Exam Week No Class
9 04/28 Network Processor Architectures
the issues of scaling and design examples

  • Chapter 14 &15
  • Chapter 12 & 13
  • Chapter 16
10 05/05  More Reviews
  1. More on Packet Processing
  2. Hardware Parallelism
  3. Software concepts
  • Ch  6,7, & 8
11 05/12 Overview of the Microengines IXP Intro
12 05/19 Classification, Forwarding  and Switching Fabrics   
13 05/26 The design tradeoffs

  • Chapter 14


14 06/02 Overview of the Programming Model (1)

  • Chapter 21
15 06/09 Overview of the Programming Model (2)

16 06/16 Project Demo/Presentation 
17 06/23 Final







  • Grading

Projects 30%
Paper Presentation 20%
Class Participation 10%
Final Exam 20%
Assignments and Homeworks 20%

Reading List

  • Network Processors
[1] K. Yi and J. Gaudiot, “Architectural Support for Network Applications on Simultaneous MultiThreading Processors,” Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International, 2007, pp. 1-10.
[2] H. Ghasemi, H. Mohammadi, B. Robatmili, and N. Yazdani, “Augmenting general purpose processors for network processing,” Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on, 2003, pp. 416-419.
[3] X. Zhuang and S. Pande, “Balancing register allocation across threads for a multithreaded network processor,” Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation, Washington DC, USA: ACM, 2004, pp. 289-300.
[4] Tzi-Cker Chiueh and P. Pradhan, “Cache memory design for network processors,” High-Performance Computer Architecture, 2000. HPCA-6. Proceedings. Sixth International Symposium on, 2000, pp. 409-418.
[5] J. Hasan, S. Chandra, and T.N. Vijaykumar, “Efficient use of memory bandwidth to improve network processor throughput,” Proceedings of the 30th annual international symposium on Computer architecture, San Diego, California: ACM, 2003, pp. 300-313.
[6] M. Peyravian and J. Calvignac, “Fundamental architectural considerations for network processors,” Comput. Netw., vol. 41, 2003, pp. 587-600.  
[7] R. Donghua, L. Chuang, C. Zhen, N. Jia, and P.D. Ungsunan, “Handling High Speed Traffic Measurement Using Network Processors,” Communication Technology, 2006. ICCT '06. International Conference on, 2006, pp. 1-5.
[8] E.A.D. Kock, “Multiprocessor mapping of process networks: a JPEG decoding case study,” Proceedings of the 15th international symposium on System Synthesis, Kyoto, Japan: ACM, 2002, pp. 68-73.
[9] G. Memik, W. Mangione-Smith, and W. Hu, “NetBench: a benchmarking suite for network processors,” Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 39-42.
[10] Xiaoning Nie, U. Nordqvist, L. Gazsi, and D. Liu, “Network processors for access network (NP4AN): trends and challenges,” SOC Conference, 2004. Proceedings. IEEE International, 2004, pp. 265-269.
[11] J. Mudigonda, H.M. Vin, and R. Yavatkar, “Overcoming the memory wall in packet processing: hammers or ladders?,” Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems, Princeton, NJ, USA: ACM, 2005, pp. 1-10.
[12] S. Govind, R. Govindarajan, and J. Kuri, “Packet Reordering in Network Processors,” Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International, 2007, pp. 1-10.
[13] “Performance Models for Network Processor Design,” IEEE Trans. Parallel Distrib. Syst., vol. 17, 2006, pp. 548-561.  
[14] C. Kulkarni, M. Gries, C. Sauer, and K. Keutzer, “Programming challenges in network processor deployment,” Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, San Jose, California, USA: ACM, 2003, pp. 178-187.
[15] J. Mudigonda, H.M. Vin, and S.W. Keckler, “Reconciling performance and programmability in networking systems,” SIGCOMM Comput. Commun. Rev., vol. 37, 2007, pp. 73-84.  
[16] V. Paxson, K. Asanović, S. Dharmapurikar, J. Lockwood, R. Pang, R. Sommer, and N. Weaver, “Rethinking hardware support for network analysis and intrusion prevention,” Proceedings of the 1st USENIX Workshop on Hot Topics in Security, Vancouver, B.C., Canada: USENIX Association, 2006, pp. 11-11.
[17] T. Wolf and Ning Weng, “Runtime Support for Multicore Packet Processing Systems,” Network, IEEE, vol. 21, 2007, pp. 29-37.  
[18] I. Papaefstathiou, G. Kornaros, and N. Zervos, “Software processing performance in network processors,” Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, pp. 186-191 Vol.3.
[19] B. Lim and M. Uddin, “Statistical-based SYN-flooding detection using programmable network processor,” Information Technology and Applications, 2005. ICITA 2005. Third International Conference on, 2005, pp. 465-470 vol.2.
[20] Chunqing Wu, Xiangquan Shi, Xuejun Yang, and Jinshu Su, “The Impact of Parallel and Multithread Mechanism on Network Processor Performance,” Grid and Cooperative Computing, 2006. GCC 2006. Fifth International Conference, 2006, pp. 236-240.
  • IP

Survey and Taxonomy of  IP Address Lookup Algorithms, IEEE Network, March/April 2001
 “The design philosophy of the DARPA internet protocols,” David D. Clark, in  Proc. of ACM SIGCOMM 88, Stanford, CA, Aug. 1988, pp. 106–114.
Using multiple hash functions to improve IP lookups, Broder, A.; Mitzenmacher, M.; INFOCOM 2001. Volume 3,  22-26 April 2001 Page(s):1454 - 1463 vol.3
Network Processors Applied to IPv4/IPv6 Transition, Eric Grosse and Lakshman Y. N., Bell Laboratories, Lucent Technologies, IEEE Network, July/August 2003
 “The IP network address translator (NAT),”  Kjeld Borch Egevang and Paul Francis, RFC 1631, Network Working Group, May 1994.
“Classless interdomain routing (CIDR): an address assignment and aggregation strategy,”  Vince Fuller, Tony Li, Jie Yun Yu, and Kannan Varadhan,  RFC 1519, Network Working Group, Sept. 1993.
  • Router & Switch Architectures


Design, Implementation and Performance of a Content-Based Switch, G. Apostolopoulos, D. et al,  INFOCOM 2000
IP Router Architectures: An Overview. James Aweya; Journal of Systems Architecture 46 (2000) pp.483-511, 1999.
Issues and trends in router design Keshav, S.; Sharma, R.; Communications Magazine, IEEE , Volume: 36 , Issue: 5 , May 1998
Pages:144 - 151


  • Network Measurement

K.C. claffy, Greg Miller, and Thompson Kevin, “The nature of the beast: Recent traffic measurements from an internet backbone,” in Proc. of 1998 INET Conference, Geneva, Switzerland, June 1998.
New Directions in Traffic Measurement and Accounting, Cristian Estan, George Varghese, SIGCOMM, August 2002
Cristian Estan, Ken Keys, David Moore, and George Varghese, “Building a better NetFlow,” in SIGCOMM ’04: Proceedings of the 2004 conference on Applications, technologies, architectures, and protocols for computer communications, Portland, OR, 2004.
Modeling Internet backbone traffic at the flow level, IEEE TRANSACTIONS ON SIGNAL PROCESSING - SPECIAL ISSUE ON NETWORKING
On the Characteristics and Origins of Internet Flow Rates, Y. Zhang and L. Breslau and V. Paxson and S. Shenker, Proceedings of ACM SIGCOMM, Aug. 2002

  • NIDS


Backtracking Algorithmic Complexity Attacks Against a NIDS, Randy Smith, Cristian Estan, Somesh Jha,  ACSAC, December 2006



  • TCP Splicing

Beyond the Network Layer: NP-Based TCP Offloading via TCP Splicing
"SpliceNP: a TCP splicer using a network processor" ANCS '05: Proceedings of the 2005 symposium on Architecture for networking and communications systems, Li Zhao and Yan Luo and Laxmi Bhuyan and Ravi Iyer


  • Content Awared Switch

A Network Processor-Based, Content-Aware Switch, Li Zhao, Yan Luo, Bhuyan, L.N., Iyer, R.  University of California, Riverside;IEEE Micro, May-June 2006


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