Network Systems Design
Emerging network packet processing applications are shifting from
routing and traffic management to those requiring inspection and
modification of packet contents. Examples include content-based
billing and quality of service, layer-7 switching, and network
security. The requirement to process every byte of a packet exceeds the
already-substantial processing capabilities of high-speed networking
Network processors (NPs) are application-specific processors that
are optimized to bridge the gap between ASIC performance and the
programmability of general-purpose processors. Most current NPs
employ multiple optimized cores, operating independently in MIMD
(Multiple Instruction stream, Multiple Data stream) fashion, usually
with multiple threads per processor to hide latency to
In this course, we are going to cover the network sytems design
and architecture exploration of the network processor.
- Upon finishing this course, students will be able to
- Understand the major hardware/software architecture for packet processing.
- Gain the concepts of network systems design by using Network Processor
- Understand the Network Processor technology and operations.
Tuesday 14:10~17:00 PM
電學507, Tuesday, 13:10~14:00PM
- Network Systems Design Using Network Processors (IXP2xxx Version) by Douglas Comer
- Students are recommended to have basic knowledge of C
programming language, microprocessor architectures, and computer
|Assignments and Homeworks
Project & Labs Resources
- Coralreef CAIDA Tools
- Network Simulator 2 (NS2)
- Intel IXP2800 SDK
- Some useful Perl resources
- The ppt slides for some tools introduced in class
- TCP splicing
- TCPSP - an open source TCP splicing implementation
||K. Yi and J. Gaudiot, “Architectural Support for Network Applications on Simultaneous MultiThreading Processors,” Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International, 2007, pp. 1-10.
||H. Ghasemi, H. Mohammadi, B.
Robatmili, and N. Yazdani, “Augmenting general purpose processors
for network processing,” Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on, 2003, pp. 416-419.
||X. Zhuang and S. Pande, “Balancing register allocation across threads for a multithreaded network processor,” Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation, Washington DC, USA: ACM, 2004, pp. 289-300.
||Tzi-Cker Chiueh and P. Pradhan, “Cache memory design for network processors,” High-Performance Computer Architecture, 2000. HPCA-6. Proceedings. Sixth International Symposium on, 2000, pp. 409-418.
||J. Hasan, S. Chandra, and T.N.
Vijaykumar, “Efficient use of memory bandwidth to improve network
processor throughput,” Proceedings of the 30th annual international symposium on Computer architecture, San Diego, California: ACM, 2003, pp. 300-313.
||M. Peyravian and J. Calvignac, “Fundamental architectural considerations for network processors,” Comput. Netw., vol. 41, 2003, pp. 587-600.
||R. Donghua, L. Chuang, C. Zhen, N.
Jia, and P.D. Ungsunan, “Handling High Speed Traffic Measurement
Using Network Processors,” Communication Technology, 2006. ICCT '06. International Conference on, 2006, pp. 1-5.
||E.A.D. Kock, “Multiprocessor mapping of process networks: a JPEG decoding case study,” Proceedings of the 15th international symposium on System Synthesis, Kyoto, Japan: ACM, 2002, pp. 68-73.
||G. Memik, W. Mangione-Smith, and W. Hu, “NetBench: a benchmarking suite for network processors,” Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 39-42.
||Xiaoning Nie, U. Nordqvist, L.
Gazsi, and D. Liu, “Network processors for access network
(NP4AN): trends and challenges,” SOC Conference, 2004. Proceedings. IEEE International, 2004, pp. 265-269.
||J. Mudigonda, H.M. Vin, and R. Yavatkar, “Overcoming the memory wall in packet processing: hammers or ladders?,” Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems, Princeton, NJ, USA: ACM, 2005, pp. 1-10.
||S. Govind, R. Govindarajan, and J. Kuri, “Packet Reordering in Network Processors,” Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International, 2007, pp. 1-10.
||“Performance Models for Network Processor Design,” IEEE Trans. Parallel Distrib. Syst., vol. 17, 2006, pp. 548-561.
||C. Kulkarni, M. Gries, C. Sauer, and K. Keutzer, “Programming challenges in network processor deployment,” Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, San Jose, California, USA: ACM, 2003, pp. 178-187.
||J. Mudigonda, H.M. Vin, and S.W. Keckler, “Reconciling performance and programmability in networking systems,” SIGCOMM Comput. Commun. Rev., vol. 37, 2007, pp. 73-84.
Paxson, K. Asanović, S. Dharmapurikar, J. Lockwood, R. Pang, R. Sommer,
and N. Weaver, “Rethinking hardware support for network analysis and
intrusion prevention,” Proceedings of the 1st USENIX Workshop on Hot Topics in Security, Vancouver, B.C., Canada: USENIX Association, 2006, pp. 11-11.
||T. Wolf and Ning Weng, “Runtime Support for Multicore Packet Processing Systems,” Network, IEEE, vol. 21, 2007, pp. 29-37.
||I. Papaefstathiou, G. Kornaros, and N. Zervos, “Software processing performance in network processors,” Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, pp. 186-191 Vol.3.
||B. Lim and M. Uddin, “Statistical-based SYN-flooding detection using programmable network processor,” Information Technology and Applications, 2005. ICITA 2005. Third International Conference on, 2005, pp. 465-470 vol.2.
Wu, Xiangquan Shi, Xuejun Yang, and Jinshu Su, “The Impact of Parallel
and Multithread Mechanism on Network Processor Performance,” Grid and Cooperative Computing, 2006. GCC 2006. Fifth International Conference, 2006, pp. 236-240.
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Router & Switch Architectures
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Router Architectures: An Overview.
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|New Directions in Traffic Measurement and Accounting, Cristian Estan, George Varghese, SIGCOMM, August 2002
|Cristian Estan, Ken Keys, David Moore, and George Varghese,
“Building a better NetFlow,” in SIGCOMM ’04:
Proceedings of the 2004 conference on Applications, technologies,
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Internet backbone traffic at the flow level, IEEE TRANSACTIONS ON SIGNAL PROCESSING - SPECIAL ISSUE ON NETWORKING
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Origins of Internet Flow Rates,
Y. Zhang and L. Breslau and V. Paxson and S. Shenker,
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|Backtracking Algorithmic Complexity Attacks Against a NIDS, Randy Smith, Cristian Estan, Somesh Jha, ACSAC, December 2006