Introduction to Digital ASIC Design
Dr. Yu-Kuen Lai
Department of Electrical Engineering
Chung Yuan Christian University
September 18, 2008
1 Course Objectives
This is an introductory level course on digital ASIC system design. Upon successfully completing the
course, student will be able to conduct cell-base ASIC design and optimization tasks. In the beginning of
this course, we will introduce the modern cell-base ASIC design flow in a top-down approach. The Verilog
hardware description language (HDL) will be covered based on the HDL grammar, coding and synthesis
guideline. The EDA tools such as logic simulator and synthesizer will be introduced as well for students in
several laboratories. We will focus on practical design methodologies including RTL simulation, synthesis,
timing analysis and design verification. In addition, we plan to use real-world design examples in the field
of computer architecture and networking for students to better comprehend the design flow and tradeoffs.
Students are required to learn state-of-the-art EDA tools and conduct several lab exercises. This is a project
oriented course. A final project with post-synthesis simulation is required at the end of the course.
Dr. Yu-Kuen Lai
*** If you want to e-mail me, please put “EE503R” in your subject line !! ***
3 Lecture Time & Place
The normal lecture is on Thursday 09:10~12:00 PM. The Lab will be held in Room 305 at the 3rd floor
of Electrical & Computer Engineering Building. Currently, the CAD tools ( Synopsys Design Compiler,
Cadence NC Verilog and Debussy) are installed in the PCs running CentOS Linux 4.4 operating system.
"Advanced Digital Design With Verilog HDL" by Michael D. Ciletti, Prentice Hall.
5 Reference books (optional)
Verilog Styles for Synthesis of Digital Systems" by David R. Smith and Paul D. Franzon, Prentice
Hall, 2000, (ISBN:0-201-61860-5)
"Verilog for Digital Design", Frank Vahid , Roman Lysecky 2007 John Wiley and Sons Publishers
"HDL Chip Design" a practical guide for designing, synthesizing and simulating ASICs and FPGAs
using VHDL or Verilog, by Douglas J. Smith, Doone Publications, 2000, (ISBN:0-9651934-3-8)
"Introduction to Computing Systems from Bits & Gates to C & Beyond", Yale N. Patt & Sanjay J.
6 Course Topics
1. Introduction to Digital ASIC Design
2. Logic Design with Verilog-Basic Language Constructs
3. Introduction to Design Environment and CAD tools
4. Introduction to Logic Synthesis-Verilog Structural & Procedural
5. Procedural Specification
6. Design Approaches for Single Modules
7. Common Problems & Mistakes
8. Logic Synthesis-Advanced Topics
9. Post Synthesis Simulation
10. Cell Characterization & Static Timing Analysis
11. Fundamental of Microprocessor Architecture
12. Introduction to FPGA
13. Hardware Functional Verification
14. Student Paper Presentation
15. Projects Presentation
7 Final Project
The purposes of doing final project is to let students gain some real-world design experiences by using the
state-of-the-art EDA tools. Students are required to design the given projects in a group of two.
More details of the project guidelines will be announced later in the class.
7.1 Some Project Topics
1. Ethernet Media Access Controller (MAC)
A simplified 3-port 10/100/1000 Ethernet Media Access Controller with 2 regular 10/100/1000
Mbps ports and a microprocessor host interface.
Based on a shared memory architecture, this MAC has to be able to perform frame validation
based on CRC-32 checking and port forwarding.
2. Microcontroller Design
LC3: This is a 16-bit microcontroller. You need to implement the complete datapath and controller
with selected instructions in the book of "Introduction to Computing Systems from Bits
& Gates to C & Beyond", Yale N. Patt & Sanjay J. Pate.
– Add 2-way set associativity cache.
– Physical Design of OpenRISC with optimization on speed, area and power.
Synthesizable VHDL Model of 8051
– European Sapce Agency IP Cores Library LEON-2 page
– Simply RISC
– OpenSPARC released by Sun Microsystems
Project of Your Own Research (Subject to instructor’s approval! )
Labs & Homeworks 30%
Final Projects /w Presentation 35%
Student Paper Presentation 15%
Midterm Exam 20%
9 Late Policy
Homeworks, Labs and projects are required to submit online to the i-learning course webpage on time. The
late submition will be deducted 10% each day.
10 Academic Integrity
Please note the existence of the University policy on academic integrity. Each assignment (lab and homework)
has to be done individually (or group) unless specified. That is, you can NOT copy other student’s
work and claim for your own.